1. Field
Exemplary embodiments relate to a digital logic circuit, and more particularly, to a digital logic circuit having a dynamic logic gate.
2. Description of the Related Art
As a need for a high-speed performance on a mobile CPU increases, logic gates adopted for logic operations of the mobile CPU increasingly become important.
General circuit design manners may make it possible to realize a stable circuit of a large noise resistance and to conduct static timing analysis (STA) relatively easily. But, the number of allowed inputs of one stage is limited, and an operating speed becomes slow due to an increase in stacks.
Meanwhile, in a circuit design manner using a dynamic logic gate, a domino gate is widely used to improve an operating speed. But, it is difficult to apply the domino gate to a conventional synthesis manner. Further, the domino gate is vulnerable to an input noise or a current leakage. One problem may arise when a keeper is used to improve the performance of the domino gate. That is, a gate delay may increase largely due to fighting.